Method of locally stressing a semiconductor layer
US9331175B2 · kind B2 · utility
1Cited by
4References
21Claims
0Family size
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Key dates
| Filing date | Aug 5, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Aug 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.