Nanodot enhanced hybrid floating gate for non-volatile memory devices
US9331181B2 · kind B2 · utility
3Cited by
25References
10Claims
0Family size
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Key dates
| Filing date | Mar 11, 2013 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Apr 21, 2034 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y40/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.