GaN device with reduced output capacitance and process for making same

US9331191B2 · kind B2 · utility

Assignee

• Efficient Power Conversion Corporation · US

Inventors

• Stephen L. Colino · Bear, US
• Jianjun Cao · Torrance, US
• Robert Beach · Altadena, US
• Alexander Lidow · Manhattan Beach, US
• Alana Nakata · Redondo Beach, US
• Guangyuan Zhao · Torrance, US
• Yanping Ma · Torrance, US
• Robert Strittmatter · Burbank, US
• Michael A. De Rooji · Palm Springs, US
• Chunhua Zhou · Suzhou, CN
• Seshadri Kolluri · San Jose, US
• Fang Liu · Toufen, TW
• Ming-Kun Chiang · Hsinchu, TW
• Jiali Cao · Torrance, US
• Agus Jauhar · Hsinchu, TW

Key dates

• Filing date: Jul 29, 2014
• Grant date: May 3, 2016
• Expiry date: Jul 29, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.