Methods and configuration for manufacturing flip chip contact (FCC) power package
US9337132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Oct 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.