Integrated circuit package testing
US9341668B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jul 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/0416
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.