Patent · US Active

Low temperature in-situ doped silicon-based conductor material for memory cell

US9343668B2 · kind B2 · utility

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Key dates

Filing dateMar 14, 2013
Grant dateMay 17, 2016
Priority date
Expiry dateMar 14, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10N70/884

Abstract

Providing for two-terminal memory cell structures and fabrication that can be achieved with a relatively low temperature process(es) is described herein. By way of example, disclosed two-terminal memory cells can be formed at least in part as a continuous deposition, potentially yielding improved efficiency in manufacturing. Furthermore, various embodiments can be compatible with some existing complementary metal oxide semiconductor fabrication processes, reducing or avoiding retooling overhead that might be associated with modifying existing fabrication processes in favor of other two-terminal memory cell fabrication techniques.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.