Coreless layer buildup structure with LGA and joining layer
US9351408B2 · kind B2 · utility
0Cited by
8References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2010 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/063
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.