Memory system including variable write burst and broadcast command scheduling
US9354823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Sep 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a memory write burst command having a first frame that includes a corresponding opcode positioned in one of a first command slot or a second command slot. The memory write burst command may also include a number of subsequent frames for conveying a data payload, as specified for example, by the opcode. The control unit may be configured to generate a number of concurrent sequential memory write operations to the memory in response to receiving the memory write burst command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.