Nanosheet MOSFET with full-height air-gap spacer
US9362355B1 · kind B1 · utility
145Cited by
12References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.