Blanket EPI super steep retrograde well formation without Si recess
US9362357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.