Overlay mark dependent dummy fill to mitigate gate height variation
US9368453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Nov 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.