Resistive memory array and fabricating method thereof
US9368552B2 · kind B2 · utility
1Cited by
4References
19Claims
0Family size
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Key dates
| Filing date | Nov 22, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Apr 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.