Method for fabricating a transistor with reduced junction leakage current

US9368624B2 · kind B2 · utility

Assignee

• Mie Fujitsu Semiconductor Limited · JP

Inventors

• Scott E. Thompson · Gainesville, US
• Lucian Shifren · San Jose, US
• Pushkar Ranade · Los Gatos, US
• Yujie Liu · Beijing, CN
• Sung Hwan Kim · Seojong-myeon, KR
• Lingquan Wang · Irvine, US
• Dalong Zhao · San Jose, US
• Teymur Bakhishev · San Jose, US
• Thomas Hoffmann · Santa Cruz, US
• Sameer Pradhan · Campbell, US
• Michael Duane · Austin, US

Key dates

• Filing date: Jul 24, 2015
• Grant date: Jun 14, 2016
• Expiry date: Jul 24, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.