CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer
US9373548B2 · kind B2 · utility
0Cited by
6References
3Claims
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Assignee
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Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Aug 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.