Adaptively limiting a maximum operating frequency in a multicore processor
US9377841B2 · kind B2 · utility
1Cited by
25References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 2013 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Mar 2, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.