Patent · US Active

Method for forming doped areas under transistor spacers

US9379213B2 · kind B2 · utility

2Cited by
1References
16Claims
0Family size

Assignees

Inventors

Key dates

Filing dateAug 4, 2014
Grant dateJun 28, 2016
Priority date—
Expiry dateAug 4, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/021
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Method for fabricating a transistor comprising the steps consisting of:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.