Method for providing charge protection to one or more dies during formation of a stacked silicon device
US9385106B1 · kind B1 · utility
5Cited by
0References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jul 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for providing charge protection to a die during formation of an integrated circuit, includes bonding the die to an interposer to form an unprotected stacked silicon component; encapsulating the unprotected stacked silicon component with a mold compound to cover at least a top surface of the die; grinding the mold compound to reduce a thickness of the mold compound; bonding a carrier wafer to the mold compound; removing the carrier wafer from the mold compound; and removing the mold compound from the top surface of the die after the carrier wafer is removed from the mold compound, to expose the top surface of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.