Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
US9385233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.