Off chip memory for distributed tessellation
US9390554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2012 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.