Patent · US Active

Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit

US9397018B2 · kind B2 · utility

3Cited by

11References

17Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ralf Otremba · Kaufbeuren, DE
Josef Hoeglauer · Munich, DE
Juergen Schredl · Mering, DE
Xaver Schloegel · Sachsenkam, DE
Wolfram Hable · Dresden, DE
Manfred Mengel · Bad Abbach, DE
Joachim Mahler · Regensburg, DE
Khalil Hosseini · Weihmichl, DE

Key dates

Filing date	Jan 16, 2013
Grant date	Jul 19, 2016
Priority date	—
Expiry date	Jan 16, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/13091
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.