Bias-temperature induced damage mitigation circuit
US9401643B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Mar 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09432
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.