Stacked memory device control
US9405468B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.