Integrated circuit and design structure having reduced through silicon via-induced stress

US9406562B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jeffrey P. Bonn · South Burlington, US
• Brent A. Goplen · Underhill, US
• Brian L. Kinsman · South Burlington, US
• Robert M. Rassel · Colchester, US
• Edmund J. Sprogis · Underhill, US
• Daniel S. Vanslette · South Burlington, US

Key dates

• Filing date: Jan 13, 2011
• Grant date: Aug 2, 2016
• Expiry date: Nov 21, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.