Semiconductor devices including superlattice depletion layer stack and related methods
US9406753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Nov 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.