Three-dimensional integrated circuit device fabrication including wafer scale membrane
US9412620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jan 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.