Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias
US9412736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jun 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.