CMOS gate contact resistance reduction
US9412759B2 · kind B2 · utility
0Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.