Semiconductor arrangement and formation thereof
US9413140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Apr 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/183
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.