Silicon germanium and silicon fins on oxide from bulk wafer
US9418900B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 15, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Jul 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.