Stacked silicon package assembly having enhanced lid adhesion
US9418909B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16196
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is provided that includes an IC die, a package substrate and a lid. The IC die is coupled to the package substrate. The lid has a first surface and a second surface. The second surface of the lid faces away from the first surface and towards the IC die. The second surface of the lid has a plurality of engineered features. The adhesive couples the plurality of engineered features of the lid to the IC die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.