Integrated circuit package and a method for manufacturing an integrated circuit package

US9425116B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Georg Meyer-Berg · Birkenfeld, DE
• Frank Daeche · Unterhaching, DE

Key dates

• Filing date: Oct 22, 2012
• Grant date: Aug 23, 2016
• Expiry date: Jun 2, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K3/4697
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact.