Capacitors in integrated circuits and methods of fabrication thereof
US9425140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2013 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Aug 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.