Dual-strained nanowire and FinFET devices with dielectric isolation
US9431539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Feb 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.