Cache coherency apparatus and method minimizing memory writeback operations
US9436605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Apr 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.