Transaction layer packet formatting

US9442855B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jasmin Ajanovic · Portland, US
• Mahesh Wagh · Portland, US
• Prashant Sethi · Folsom, US
• Debendra Das Sharma · Saratoga, US
• David J. Harriman · Sacramento, US
• Mark Rosenbluth · Uxbridge, US
• Ajay V. Bhatt · Portland, US
• Peter Barry · Limerick, IE
• Scott Dion Rodgers · Hillsboro, US
• Anil Vasudevan · Portland, US
• Sridhar Muthrasanallur · Tumwater, US
• James Akiyama · Beaverton, US
• Robert G. Blankenship · Tacoma, US
• Ohad Falik · Kfar Sava, IL
• Avi Mendelson · Haifa, IL
• Ilan Pardo · Ramat HaSharon, IL
• Eran Tamari · Ramat Gan, IL
• Eliezer Weissmann · Haifa, IL
• Doron Shamia · Holon, IL

Key dates

• Filing date: Dec 27, 2014
• Grant date: Sep 13, 2016
• Expiry date: Dec 27, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/621
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.