Material processing to achieve sub-10nm patterning
US9443731B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Feb 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a cap layer of a second composition formed atop said structure. The sidewall is exposed to a chemical environment and creates a chemically modified sidewall layer of a third composition. The cap layer and an interior, non-modified portion of said structure is removed using an etching process to leave behind said chemically modified sidewall layer. A pattern transfer etch of said sidewall chemically modified layer onto the underlying layer of said substrate is performed. One or more integration operating variables are controlled to achieve target critical dimensions comprising width, height, sidewall angle, line width roughness, and/or line edge roughness of said structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.