System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset
US9449651B2 · kind B2 · utility
3Cited by
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20Claims
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Key dates
| Filing date | Mar 20, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Mar 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end is disclosed. According to one embodiment, a CPIO ASIC provides variable timing control for its DDR-4 LRDIMM interface such that propagation delay of the data buffers can be offset by the CPIO ASIC, allowing the CPIO LRDIMM to be timing compatible with an RDIMM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.