Cross-coupled thyristor SRAM circuits and methods of operation
US9449669B2 · kind B2 · utility
13Cited by
17References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/131
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.