3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

US9449913B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kevin J. Lee · Beaverton, US
• Mark Bohr · Beaverton, US
• Andrew W. Yeoh · Portland, US
• Christopher M. Pelto · Beaverton, US
• Hiten Kothari · Beaverton, US
• Seshu V. Sattiraju · Portland, US
• Hang-Shing Ma · Portland, US

Key dates

• Filing date: Oct 28, 2011
• Grant date: Sep 20, 2016
• Expiry date: Jul 19, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1461
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.