Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern
US9449943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2014 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jul 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.