Memory cell with high-k charge trapping layer
US9449985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | May 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.