EEPROM memory cell with low voltage read path and high voltage erase/write path
US9455037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Mar 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.