Integrated circuit package and method of forming the same
US9455241B2 · kind B2 · utility
0Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.