Protecting memory interface
US9455962B2 · kind B2 · utility
1Cited by
29References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2014 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Aug 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/0428
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.