Two-transistor thyristor SRAM circuit and methods of operation
US9460771B2 · kind B2 · utility
8Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jan 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with the thyristor in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.