Memory cell having a vertical selection gate formed in an FDSOI substrate
US9461129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Sep 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.