Multi-polygon constraint decomposition techniques for use in double patterning applications
US9465907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Aug 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.