Integrated circuit
US9466363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2012 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | May 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation:τ>λ1/f1(0<λ1≦1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.