Memory device with secure test mode
US9471413B2 · kind B2 · utility
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6References
8Claims
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Key dates
| Filing date | Jan 24, 2016 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jan 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.