Methods of forming a nanowire transistor device
US9484407B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Aug 27, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Aug 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.